A “flip chip” package, “wire bond” package and multi-stacked die technology refer to integrated circuits that include at least one semiconductor die, which is bonded to a substrate. In a flip chip package, a semiconductor is bonded circuit-side down to the substrate, with direct electrical interconnection between the die and the substrate. In a wire bond package, the semiconductor die is bonded to the substrate with electrical leads from the die connecting to the substrate around the periphery of the die.
The substrate can be a passive carrier such as a printed circuit board, or it can be another semiconductor chip. The substrate is normally bonded directly to a motherboard. Other flip chips and other integrated circuits employing a variety of more traditional packages, such as lead frame packages, surface mounts, pin grid arrays and the like can also be mounted to the motherboard.
One purpose that the substrate serves is to allow the input-output (I/O) signals on the die to “escape” the die onto the motherboard and to provide electrical power to the die from the motherboard. Die are usually quite small, and contain as many as hundreds of I/O signals as well as numerous power and ground connections. There can be “bumps” (e.g., solder spheres) on the surface pads of the die to facilitate electrical connections to the substrate. Since these bumps are densely packed together onto the small die, it may not be practical to attempt to bond such tightly packed bumps to a motherboard. The substrate serves the purpose of spreading-out these densely packed bumps to a much less dense spacing, so that the I/O signals and power and ground connections can then be connected to the motherboard.
When a flip chip die is mounted to a substrate, the bumps on the die are the points of physical and electrical contact between the die and the substrate. The bumps carry electrical signals including power and ground to and from the die. The substrate has a surface, typically the surface opposite the side on which the die is mounted, which has a plurality of contacts called pads or lands. A solder ball is typically attached to each land for soldering to the motherboard. The solder balls are collectively referred to as a ball grid array, because they are usually arranged in a grid pattern. A “ball assignment scheme” is a pattern in which the balls for the I/O signals and power and ground connections are assigned on the substrate.
Each I/O bump in the die bonding area is directly connected to a corresponding ball in the ball grid array on the other surface of the substrate through conductive segments called “traces” along one or more layers in the substrate and through one or more “vias” between the layers.
Recent silicon technology advances demand higher performance package designs. For example as the core voltage level reduces with each successive generation of silicon, there is a desire to further reduce noise in the core voltage plane. It is therefore desirable for the substrate design to have a large number of core voltage supply vias (e.g., VSSCORE and VDDCORE) that are electrically coupled in order to reduce core plane impedance so that core noise is minimized. On a semiconductor die, the devices that are biased at the low core voltage levels are typically located in a central area of the die. Therefore, vias in the substrate that supply the core voltage to the die are typically arranged on the substrate in a grid pattern under the center of the die. Maximizing the density of the core voltage supply vias under the center of die therefore requires the vias to be added at a minimum possible pitch.
A typical via layout attempts to maximize the number of core voltage supply vias to provide good electrical coupling between the vias leading to a low impedance connection. However, the wall-to-wall distance between power and ground vias can therefore be small. When a via is “drilled” through a material that has woven glass fiber reinforcements running in a typical orthogonal pattern, there is a possibility for glass fibers to line up from one via wall to the next. Under typical field operating conditions, in the presence of humidity and a voltage bias between the core power and ground vias, copper migration can occur from the via wall of the anode (a core power via) to the via wall of the cathode (a core ground via). Copper migration can cause a conductive path to develop leading to failure in the field or during reliability testing, which is a time and temperature dependent variable.
One existing solution is to reduce the number of core voltage supply vias to increase the spacing between core power vias and core ground vias. However, this solution increases core impedance due to the lower number of vias.
Another difficulty encountered with via layouts is that the grid via pattern and the core power and ground via assignments can lead to lower manufacturing yield for the supplier due to a need to electrically isolate the densely packed core power and ground vias.
Improved via layout patterns for substrates are therefore desired.